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Physical Design (PD) Engineers

  • On-site, Hybrid
    • Rawabi, Nablus & Hebron, Ramallah, Palestine, State of
  • Service Delivery

Job description

About ASAL:

ASAL Technologies was established in 2000 and has grown to become a leading technology company across Jordan, KSA, UAE, and Palestine. With a workforce of over 450 engineers, ASAL offers a wide range of AI agents, services and products, Software and Digital Transformation services, Engineering and R&D services. ASAL Technologies is assembling a team of PD Engineers for a high-end multinational company. The team will be working with top notch engineers in the semiconductor industry from all over the world.

 

About the Role:

We are seeking highly skilled and detail-oriented Physical Design (PD) Engineers to join our silicon development team. In this role, you will be responsible for transforming complex digital circuit from (RTL / netlists) into (GDSII).

You will collaborate closely with design, architecture, and DFT (Design for Test) teams to achieve aggressive Performance, Power, and Area (PPA) targets for next-generation chips.

Key Responsibilities:

  • Full Flow Execution: Drive block-level and chip-level implementation through the entire RTL-to-GDSII flow, including floor planning, placement, Clock Tree Synthesis (CTS), routing, and physical verification.

  • PPA Optimization: Identify and resolve critical path timing issues, optimize routing congestion, and minimize power consumption (both static and dynamic leakage).

  • Timing & Sign-off: Perform Static Timing Analysis (STA) across multiple process corners, manage constraints, and execute timing closure.

  • Physical Verification: Validate designs against industry standards using Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checking (ERC) to ensure high-yield manufacturing.

  • Flow Automation: Develop, maintain, and optimize design flow automation scripts to improve turnaround time and efficiency.

Job requirements

Required Skills & Qualifications:

  • Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

  • Core Engineering: Deep understanding of VLSI and CMOS technology, deep-submicron process effects, static timing analysis concepts, and digital logic design.

  • EDA Tool Proficiency: Hands-on experience with major industry-standard Physical Design tools (e.g., Synopsys / Cadence ) — Innovus / IC Compiler II, PrimeTime, Calibre.

  • Scripting Capabilities: Strong scripting skills in TCL, Python, or Perl for tool automation and productivity enhancement.

  • Strong written and verbal English skills.

 

Application Deadline: 21-09-2026

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